I'm following TI's C2000 GUI Composer tutorial to create a GUI composer project. On the first page of the New Project Wizard, I'm asked to upload "desktop shortcut icon" and "Window icon". The "Next" ...

I need to run debug on an old product. I have the tools and connectors used at the time development was done on it but cannot get the JTAG communication running. I'm using a MSP-FET430UIF (grey box) ...

设置SPI多个片选引脚除了config里面定义的其余引脚是否需要用GPIO虚拟，同时虚拟出来的引脚对传输速率是否有影响 可以使用GPIO模拟，在每次SPI发送之前，对SPI的片选信号也会进行控制，所以SPI ...

I think i have identified a discrepancy in the documentation of the MSTGENA field descriptions for the Memory Self-Test Controller Global Enable Key. This needs to be reviewed and corrected to align ...

I am stacking two BQ76952 ICs and interfacing them to an MCU using SPI. IC-1 is powered from cells 1-16. IC-2 is powered from 17-19. Both ICs are interfaced with MCU using a single SPI module and ...

I am trying to implement state machine based tasks in 28027. I referred some programmes given in control suite. I am however not able to go between various tasks A0, A1, A2 etc. What could be the ...

Hi I want to get an interrupt when a SPI reception finished. My setup is the following. I have an SPI D configured as master with loopback mode. My actual application will be configured as slave but ...

Understanding these aspects is crucial for our project and system stability. Any insights or additional documentation you could provide would be highly valuable. Thank you for your assistance.

I used cascade_radar_object_detect to capture the point cloud data from the 4-cascade 2243 radar and used TFDTP to receive the data. When I set the cascade radar's FRAME_PERIODICITY to 50ms, there was ...

I'm currently using the "h264_v4l2m2m" hw encoder to encode video in h264 format on TDA4 with the ffmpeg library and stream it using TCP. The problem I'm facing is that I cannot join the stream in the ...

I have a situation where 4 of the ADC3664 devices will be used in a design. The devices will operate from the same input clock source and are intended to be synchronous. My question is: can the FPGA ...

I am configuring a new laptop with TI development tools, using the same products as on an older computer. The older computer has been running CCS version 12.4 and C2000ware version 5.02.00.00 for over ...